Module Tjr_kv

tjr_kv: A key-value store (example instance)

include Tjr_kv__.Summary

Architecture

See Kv_store_with_lru for more details

Main interfaces

module type S = sig
  type k[@@deriving bin_io]
  type v[@@deriving bin_io]
  val k_cmp: k -> k -> int
  type r = Shared_ctxt.r[@@deriving bin_io]

  val k_size: int
  val v_size: int
  val r_size: int
end
module type S' = sig
  (* NOTE specialized to shared_ctxt *)
  type k
  type v
  val k_cmp: k -> k -> int
  val k_mshlr: k bp_mshlr
  val v_mshlr: v bp_mshlr
end

type ('k,'v) kv_store = <
  blk_alloc     : (r, t) blk_allocator_ops;
  btree_thread  : < start_btree_thread : unit -> (unit, t)m >;
  lru_ops       : ('k, 'v, t) mt_ops;
  min_free      : min_free;
  pcache_thread : < start_pcache_thread : unit -> (unit, t)m >;
  q_lru_pc      : ('k, 'v, t) q_lru_pc;
  q_pc_bt       : ('k, 'v, t) q_pc_bt;
  root_man      : (rt_blk, t) root_man; 
  rt_blk        : rt_blk 
>
module Kv_intf : sig ... end

Main types

Configuration and profilers

module Kv_config_optcomp : sig ... end
module Kv_config_runtime : sig ... end
module Kv_config_profilers : sig ... end

Root manager

module Root_manager : sig ... end

Btree thread

module Btree_thread : sig ... end

The B-tree worker thread; don't open

Pcache thread

module Pcache_thread : sig ... end

Pcache worker thread, which takes an existing pcache_ops, wraps it using blocks limit, and interfaces with the B-tree

Lru

module Lru = Lru

The key-value store

module Kv_store_with_lru : sig ... end

A KV store with an LRU cache frontend.

Further notes

Combining B-tree and pcache roots in a single block

One option when syncing the btree+pcache combination would be to write the pcache roots to disk, and then (in another block) write the B-tree root. This is fine, but if a crash occurs inbetween, we have to recover (which isn't difficult, but still adds complexity). As an alternative, we can write the btree and the pcache roots into the same block atomically. This means that we don't have to worry about recovering from a crash (this approach is crash safe by design).